I. Field of the Disclosure
The technology of the disclosure relates generally to optimization of execution pipelines in out-of-order (OOO) computer processors, and in particular, to selective reconfiguration of execution pipelines.
II. Background
Out-of-order (OOO) computer processors are processors that are capable of executing computer program instructions in an order determined by an availability of input operands for each instruction, regardless of the order of appearance of the instructions in the computer program. By executing instructions out of order, an OOO computer processor may be able to fully utilize processor clock cycles that would otherwise be wasted while the OOO computer processor waits for data access operations to complete. For example, instead of having to “stall” (i.e., intentionally introduce a processing delay) instructions in an execution pipeline while input data is retrieved for an older program instruction, the OOO computer processor may proceed with executing a more recently fetched instruction that is able to execute immediately. In this manner, processor clock cycles may be more productively utilized by the OOO computer processor, resulting in an increase in the number of instructions that the OOO computer processor is capable of processing per processor clock cycle.
In a conventional OOO computer processor, the “back-end pipeline” of each execution pipeline includes hardware that enables such functionality as register renaming, register file access, booking into reservation stations (RSVs), booking into and committing out of instruction ordering structures, instruction wakeup and selection from the RSVs, and instruction execution by execution units (e.g., Arithmetic Logic Units (ALUs)). Because the back-end pipeline is designed to extract maximum performance in all program phases, it may be overprovisioned in program phases having low instruction-level parallelism, a large number of mispredicted branches, and/or a large number of instruction refetching due to hazards, as non-limiting examples. This may result in higher processor power consumption, which in turn may reduce battery life and reliability, and may increase the cost for power delivery network design, packaging, and cooling.
One conventional technique for reducing power consumption is to proportionately reduce the performance of the OOO computer processor. However, processor performance requirements have increased with every new generation of OOO computer processors. Consequently, intentionally degrading processor performance as a power-saving technique is not an ideal solution. It is thus desirable to provide a mechanism for improving energy efficiency by reducing the power consumption of back-end pipelines in OOO computer processors with minimal performance loss.